Network-On-Chip Mesh Topology Modeling Performance Analysis

Siti Aisah , Mat Junos @ Yunus (2009) Network-On-Chip Mesh Topology Modeling Performance Analysis. Masters thesis, Universiti Teknologi Malaysia.

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Abstract

A Network-on-Chip (NoC) is a new paradigm in complex System-on-Chip (SoC) designs that provide efficient on-chip communication architecture. It offers scalable communication and allows decoupling of communication and computation. Instead of passing data through circuit-switching, data is routed in packets. In an NoC design, design space exploration is critical due to trade-offs between latency, area, and power consumption. Hence, analytical modeling is an important step for early NoC design space exploration. This project report presents a performance analysis in term of throughput, average queue size, efficiency, loss, and wait time for an application specific mesh NoC. Top-down approach is used to model a queue, router, and mesh NoC. The experimental case study of video applications MPEG4 core is mapped to a 4x4 mesh NoC with deterministic routing to estimate the overall NoC performance. From this model, the performance of each router is shown in detail, hence, queue and router hotspots can be determined in the NoC topology. This modeling also details the occupancy of routers' queue to reflect the used area and cost. Modeling an NoC topology according to the application gives an estimate on NoC performance before actual design begins.

Item Type: Thesis (Masters)
Uncontrolled Keywords: Networks on a chip, Microelectronics, Embedded computer systems
Subjects: T Technology > T Technology (General)
T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Library > Tesis > FKEKK
Depositing User: Siti Syahirah Ab Rahim
Date Deposited: 18 Jul 2014 11:49
Last Modified: 28 May 2015 04:28
URI: http://eprints.utem.edu.my/id/eprint/12931
Statistic Details: View Download Statistic

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