Redundant Residue Number System Code for Fault-Tolerant Hybrid Memories

Haron, Nor Zaidi (2011) Redundant Residue Number System Code for Fault-Tolerant Hybrid Memories. ACM Journal on Emerging Technologies in Computing Systems, 1 (1). pp. 1-19. ISSN 1550-4832

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Hybrid memories are envisioned as one of the alternatives to existing semiconductor memories. Although offering enormous data storage capacity, low power consumption, and reduced fabrication complexity (at least for the memory cell array), such memories are subject to a high degree of intermittent and transient faults leading to reliability issues. This article examines the use of Conventional Redundant Residue Number System (C-RRNS) error correction code, which has been extensively used in digital signal processing and communication, to detect and correct intermittent and transient cluster faults in hybrid memories. It introduces a modified version of C-RRNS, referred to as 6M-RRNS, to realize the aims at lower area overhead and performance penalty. The experimental results show that 6M-RRNS realizes a competitive error correction capability, provides larger data storage capacity, and offers higher decoding performance as compared to C-RRNS and Reed-Solomon (RS) codes. For instance, for 64-bit hybrid memories at 10% fault rate, 6MRRNS has 98.95% error correction capability, which is 0.35% better than RS and 0.40% less than C-RRNS. Moreover, when considering 1Tbit memory, 6M-RRNS offers 4.35% more data storage capacity than RS and 11.41% more than C-RRNS. Additionally, it decodes up to 5.25 times faster than C-RRNS.

Item Type: Article
Uncontrolled Keywords: Hybrid memories, nanowire, residue number system, fault-tolerance, error correction codes
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Faculty of Electronics and Computer Engineering > Department of Computer Engineering
Depositing User: Dr Nor Zaidi Haron
Date Deposited: 09 Jul 2012 07:07
Last Modified: 24 Nov 2021 17:39
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