Simplified VHDL Coding of Modified Non-Restoring Square Root Calculator

Jidin, Auzani (2012) Simplified VHDL Coding of Modified Non-Restoring Square Root Calculator. International Journal of Reconfigurable and Embedded Systems (IJRES). pp. 37-42. ISSN 2089-4864

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Square root calculation is one of the most useful and vital operation in digital signal processing which in recent generations of processors, the operation is performed by the hardware. The hardware implementation of the square root operation can be achieved by different means, but it is very dependent on programmer's sense and ability to write efficient hardware designs. This paper offers universal and shortest VHDL coding of modified non-restoring square root calculator. The main principle of the method is similar with conventional non-restoring algorithm, but it only uses subtract operation and append 01, while add operation and append 11 is not used. The strategy has conducted to implement successfully in FPGA hardware, and offer an efficient in hardware resource, and it is superior.

Item Type: Article
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Faculty of Electrical Engineering > Department of Power Electronics & Drives
Depositing User: Dr Auzani Jidin
Date Deposited: 20 Aug 2013 09:01
Last Modified: 28 May 2015 03:59
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