NBTI degradation effect on advanced-process 45 nm high-k PMOSFETs with geometric and process.

Wan Muhamad Hatta, S.F. and Soin, N. and Abd Hadi, D. and Zhang, J.F. (2010) NBTI degradation effect on advanced-process 45 nm high-k PMOSFETs with geometric and process. Microelectronics Reliability, 50 (9-11). pp. 1283-1289. ISSN 0026-2714

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Abstract

Negative bias temperature instability (NBTI) has become an important reliability concern for nano-scaled complementary metal oxide (CMOS) devices. This paper presents the effect of NBTI for a 45 nmadvanced process high-k dielectric with metal gate PMOS transistor. The device had incorporated advanced-process flow steps such as stress engineering and laser annealing in order to achieve high on-state drain current drive performance. To explore NBTI effects on an advanced-process sub-micron device, the 45 nm high-k PMOS transistor was simulated extensively with a wide range of geometric and process variations. The device was simulated at varying thicknesses in the dielectric layer, oxide interfacial layer, metal gate and polysilicon layer. In order to observe the NBTI effect on process variation, the NBTI degradation of the 45 nm advanced-process PMOS is compared with a 45 nm PMOS device which does not employ process-induced stress and incorporates the conventional rapid thermal annealing (RTA) as compared to the laser annealing process which is integrated in the advanced-process device flow. The simulation results show increasing degradation trend in terms of the drain current and threshold voltage shift when the thicknesses of the dielectric layer, oxide layer as well as the metal gate are increased.

Item Type: Article
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Depositing User: Cik Dayanasari Abdul hadi
Date Deposited: 08 Oct 2012 04:02
Last Modified: 28 May 2015 03:33
URI: http://eprints.utem.edu.my/id/eprint/5338
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