Influence of HALO and source/drain implantation on threshold voltage in 45nm PMOS device

Fauziyah, Salehuddin and Ahmad, Ibrahim and Fazrena, Azlee Hamid and Azami , Zaharim (2011) Influence of HALO and source/drain implantation on threshold voltage in 45nm PMOS device. Australian Journal of Basic and Applied Sciences, 5 (1). pp. 55-61. ISSN 1991-8178

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In this paper, we investigate the influence of process parameters like HALO and Source/Drain (S/D) Implantation on threshold voltage in 45nm PMOS device. The settings of process parameters were determined by using Taguchi experimental design method. The level of importance of the process parameters on threshold voltage was determined by using analysis of variance (ANOVA). The virtual fabrication of the PMOS device was performed by using ATHENA module. While the electrical characterization of the device was implemented by using ATLAS module. These two modules were combined with Taguchi method to aid in design and optimizer the process parameters. Besides HALO and S/D implantation, the other two process parameters which used were oxide growth temperature and silicide anneal temperature. These process parameters were varied for 3 levels to perform 9 experiments. Threshold voltage (VTH) results were used as the evaluation variables. Then, the results were subjected to the Taguchi method to determine the optimal process parameters and to produce predicted values. The predicted values of the process parameters were verified successfully with ATHENA and ATLAS's simulator. In this research, halo implantation found to be the major factor affecting the threshold voltage (70%), whereas silicide anneal temperature was the second ranking factor (17%). As conclusions, halo implantation was identified as one of the process parameters that has the strongest effect on the response characteristics. While the S/D Implantation was identified as an adjustment factor to get the threshold voltage closer to the nominal value (-0.150V).

Item Type: Article
Uncontrolled Keywords: component, 45nm PMOS device, HALO, S/D implantation, threshold voltage, Taguchi Method
Subjects: T Technology > TA Engineering (General). Civil engineering (General)
Divisions: Faculty of Electronics and Computer Engineering > Department of Computer Engineering
Depositing User: Mrs Fauziyah Salehuddin
Date Deposited: 30 Mar 2015 01:52
Last Modified: 28 May 2015 04:11
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