Zainodin, Aznilinda and Ab. Kadir, Aida Khairunnisaa and Ayob, M Nasir and Hassan, Ahmad Fariz and Zainal Abidin, Amar Faiz and Zahid, Fazlinashatul Suhaidah and Jaafar, Hazriq Izzuan and Mohd Khairuddin, Ismail (2014) An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm. In: Colloquium on Robotics, Unmanned Systems And Cybernetics 2014 (CRUSC 2014), 20 November 2014, Universiti Malaysia Pahang, Pekan, Pahang, Malaysia.
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Abstract
Combinatorial logic circuit minimization is usually done using Karnaugh’s Map or Boolean equation. This paper presents an application of Firefly Algorithm to design combinational logic circuit in which the objective function is to minimize the total number of gates used. Then, the algorithm is benchmarked with other literatures. Result indicates that it able to find optimal solution but further analysis is required for a more complex combinatorial logic circuit minimization.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering |
| Divisions: | Faculty of Electrical Engineering > Department of Control, Instrumentation & Automation |
| Depositing User: | HAZRIQ IZZUAN JAAFAR |
| Date Deposited: | 25 Nov 2014 11:52 |
| Last Modified: | 28 May 2015 04:34 |
| URI: | http://eprints.utem.edu.my/id/eprint/13783 |
| Statistic Details: | View Download Statistic |
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