A DFT technique for electrical interconnect testing of circuit boards with 3D Stacked SRAM ICs

Ikiri, Yuki and Yotsuyanagi, Hiroyuki and Ali, Fara Ashikin and Lu, Shyue-Kung and Hashizume, Masaki (2023) A DFT technique for electrical interconnect testing of circuit boards with 3D Stacked SRAM ICs. In: 12th IEEE CPMT Symposium Japan, ICSJ 2023, 15 November 2023 through 17 November 2023, Kyoto.

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Abstract

A Design-for-test (DfT) technique is proposed in this paper for a test method, by which detecting open defects occurring interconnects between 3D stacked SRAM IC and a printed circuit board and among dies inside them. The test method is based on the supply current that is made flow through an interconnect to be tested. The DfT technique utilizes a built- in current sensor circuit to detect the open defects. It is shown that open defects occurring at interconnects among dies designed by the DfT method in a 3D stacked SRAM IC, and between the IC and a circuit board can be detected by the supply current test method.

Item Type:	Conference or Workshop Item (Paper)
Uncontrolled Keywords:	Interconnect test ,3D memory IC, Open defect ,SRAM, Assembled circuit board
Divisions:	Faculty Of Electronics And Computer Technology And Engineering
Depositing User:	Anis Suraya Nordin
Date Deposited:	17 Oct 2024 16:19
Last Modified:	17 Oct 2024 16:19
URI:	http://eprints.utem.edu.my/id/eprint/28088
Statistic Details:	View Download Statistic

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