On Defect Oriented Testing for Hybrid CMOS/memristor Memory

Haron, Nor Zaidi and Hamdioui, Said (2011) On Defect Oriented Testing for Hybrid CMOS/memristor Memory. In: Asian Test Symposium 2011, 20-23 November 2011, New Delhi.

[img] PDF (Proceedings)
NZBHaron_ATS11.pdf - Published Version
Restricted to Repository staff only

Download (281kB) | Request a copy


Hybrid CMOS/memristor memory (hybrid memory) technology is one of the emerging memory technologies potentially to replace conventional non-volatile flash memory. Existing research on such novel circuits focuses mainly on the integration between CMOS and non-CMOS, fabrication techniques and reliability improvement. However, research on defect analysis for yield and quality improvement is still in its infancy stage. This paper presents a framework of defect oriented testing in hybrid memory based on electrical simulation. First, a classification and definition of defects is introduced. Second, a simulation model for defect injection and circuit simulation is proposed. Third, a case study to illustrate how the proposed approach can be used to analyze the defects and translate their electrical faulty behavior into fault models - in order to develop the appropriate tests and design for testability schemes - is provided. The simulation results show that in addition to the occurrence of conventional semiconductor memories faults, new unique faults take place, e.g., faults that cause the cell to hold an undefined state. These new unique faults require new test approaches (e.g., DfT) in order to be able to detect them.

Item Type: Conference or Workshop Item (Paper)
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Faculty of Electrical Engineering > Department of Industrial Power
Depositing User: Dr Nor Zaidi Haron
Date Deposited: 10 Jul 2012 04:06
Last Modified: 28 May 2015 02:37
URI: http://eprints.utem.edu.my/id/eprint/3758
Statistic Details: View Download Statistic

Actions (login required)

View Item View Item