Design of Gain Booster for Sample and Hold Stage of High Speed-Low Power Pipelined Analog-To-Digital Converter

Jali, Mohd Hafiz (2013) Design of Gain Booster for Sample and Hold Stage of High Speed-Low Power Pipelined Analog-To-Digital Converter. Journal of telecommunication, electronic and computer engineering , 5 (1). pp. 23-30. ISSN 2180-1843

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Abstract

This paper presents the full custom design of an operational transconductance amplifier (OTA) for the sample and hold (SHA) stage of a 10-bit 50-MS/s pipelined analog-to-digital converter (ADC) implemented in a TSMC 0.35μm CMOS process. The OTA chosen for this design is folded cascode with gain boost topology. It is demonstrated through the design analysis and HSPICE simulation that such a structure realizes the best trade-off between power, speed and gain. The simulation results show the OTA achieves DC gain of 88.05dB, unity gain bandwidth of 430.03MHz and 84.06 degree of phase margin. The OTA achieves 62.13 dB SNR at the sampling rate of 50MHz with the input frequency of 24MHz. Power consumption is 9.68 mW from a single 3V supply. The settling time to 2-11 accuracy is 8.2ns.

Item Type:	Article
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:	Faculty of Electrical Engineering > Department of Diploma Studies
Depositing User:	MOHD HAFIZ JALI
Date Deposited:	05 Aug 2013 01:08
Last Modified:	28 May 2015 04:01
URI:	http://eprints.utem.edu.my/id/eprint/9110
Statistic Details:	View Download Statistic

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