Haron, Nor Zaidi and Md Junos@Yunus, Siti Aisah and Abdul Aziz, Amir Shah (2007) Modeling And Simulation Of Microcode Memory Built-in Self Test Architecture For Embedded Memories. In: 2007 International Symposium on Communications and Information Technologies (ISCIT 2007), -, -.
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Modeling And Simulation Of Microcode Memory Built-in Self Test Architecture For Embedded Memories.pdf - Submitted Version Restricted to Repository staff only Download (2MB) |
Abstract
Memory Built-In Self Test (MBIST) or as some refer to it array built-in self-test is an amazing piece of logic. Without any direct connection to the outside world, a very complex embedded memory can be tested efficiently, easily and less costly. Modeling and simulation of Microcode MBIST is presented in this paper. The design architecture is written using Very High Speed Integrated Circuit Hardware Description Language (VHDL) code using Xilinx ISE tools. The architecture is modeled and synthesized using register transfer level (RTL) abstraction. Verification of this architecture is carried out by testing stuck at fault SRAM. Five BIST algorithms are implemented i.e MATS, MATS+, MARCH X, MARCH C and March C- to test the faulty SRAM.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Subjects: | T Technology > T Technology (General) |
| Divisions: | Faculty of Electronics and Computer Engineering |
| Depositing User: | Muhammad Afiz Ahmad |
| Date Deposited: | 15 Dec 2017 00:35 |
| Last Modified: | 15 Dec 2017 00:35 |
| URI: | http://eprints.utem.edu.my/id/eprint/20192 |
| Statistic Details: | View Download Statistic |
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