Geometric And Process Design Of Ultra-Thin Junctionless Double Gate Vertical MOSFETs

Salehuddin, Fauziyah and Kaharudin, Khairil Ezwan and Mohd Zain, Anis Suhaila and Roslan, Ameer Farhan (2019) Geometric And Process Design Of Ultra-Thin Junctionless Double Gate Vertical MOSFETs. International Journal of Electrical and Computer Engineering, 9 (4). pp. 2863-2873. ISSN 2088-8708

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Abstract

The junctionless MOSFET architectures appear to be attractive in realizing the Moore's law prediction. In this paper, a comprehensive 2-D simulation on junctionless vertical double-gate MOSFET (JLDGVM) under geometric and process consideration was introduced in order to obtain excellent electrical characteristics. Geometrical designs such as channel length (Lch) and pillar thickness (Tp) were considered and the impact on the electrical performance was analyzed. The influence of doping concentration and metal gate work function (WF) were further investigated for achieving better performance. The results show that the shorter Lch can boost the drain current (ID) of n-JLDGVM and p-JLDGVM by approximately 68% and 70% respectively. The ID of the n-JLVDGM and p-JLVDGM could possibly boost up to 42% and 78% respectively as the Tp is scaled down from 11nm to 8nm. The channel doping (Nch) is also a critical parameter, affecting the electrical performance of both n-JLDGVM and p-JLDGVM in which 15% and 39% improvements are observed in their respective ID as the concentration level is increased from 1E18 to 9E18 atom/cm3. In addition, the adjustment of threshold voltage can be realized by varying the metal WF.

Item Type:	Article
Uncontrolled Keywords:	Channel doping, Channel length, Doping concentration, Pillar thickness, Source/drain doping, Work function, MOSFETs
Divisions:	Faculty of Electronics and Computer Engineering
Depositing User:	Sabariah Ismail
Date Deposited:	30 Jul 2020 10:06
Last Modified:	30 Jul 2020 10:06
URI:	http://eprints.utem.edu.my/id/eprint/24222
Statistic Details:	View Download Statistic

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