Application of Taguchi Method in Optimization of Gate Oxide and Silicide Thickness for 45nm NMOS Device

Fauziyah, Salehuddin (2009) Application of Taguchi Method in Optimization of Gate Oxide and Silicide Thickness for 45nm NMOS Device. International Journal of Engineering & Technology, 9 (10). pp. 94-98. ISSN 2077-1185 (Online) 2227-2712 (Print)

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Abstract

The optimization of 45nm NMOS device was studied using Taguchi Method. This method was used to analyze the experimental data in order to get the optimum results. In this paper, there are four factors were varied for 3 levels to perform 9 experiments. Silicide on the poly-Si gate electrode was used to reduce the gate electrode resistance. The virtually fabrication of 45nm NMOS device was performed by using ATHENA module. While the electrical characterization of device was implemented by using ATLAS module. The values of oxide and silicide thickness after optimization approach were 1.52709nm and 25.26nm respectively. The result of the threshold voltage (VTH) is 0.148468 Volts. In this research, silicide thickness and oxide thickness are the main factors were identified as the source of the inability of the transistors to perform. The oxide thickness also was identified as one of the factors that has the strongest effect on the response characteristics.

Item Type:	Article
Uncontrolled Keywords:	Optimization of 45nm nMOS, Cobalt Silicide, Taguchi Method
Subjects:	T Technology > TA Engineering (General). Civil engineering (General)
Divisions:	Faculty of Electronics and Computer Engineering > Department of Computer Engineering
Depositing User:	Mrs Fauziyah Salehuddin
Date Deposited:	10 Jul 2012 01:48
Last Modified:	25 Nov 2021 12:04
URI:	http://eprints.utem.edu.my/id/eprint/3792
Statistic Details:	View Download Statistic

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