Implementation Of SVM For Cascaded H-Bridge Multilevel Inverters Utilizing FPGA

Al-Jewari, Maher Abd Ibrahim (2019) Implementation Of SVM For Cascaded H-Bridge Multilevel Inverters Utilizing FPGA. Masters thesis, Universiti Teknikal Malaysia Melaka.

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Abstract

In recent years the Space Vector Modulation (SVM) technique has gained wide acceptance for many AC drive applications. Further improvements of AC drives can be accomplished by applying SVM in multilevel inverters, since the more suitable voltage vectors can be chosen among larger number of voltage vectors available in the multileve inverter. However, the use of multilevel inverters associated with SVM by using Digital Signal Processor (DSP) increases the complexity of control algorithm or computational burden and hence produces larger value of sampling time. This thesis reports the implementation of SVM in Cascaded H-Bridge Multilevel Inverter (CHMI) using Field Programmable Gate Arrays (FPGA) and analysis in-depth the performances of SVM computation on THD and fundamental component of output voltage. The SVM modulator is modelled using MATLAB/Simulink, which is sampled at the minimum sampling time, i.e. DT = 5 us. The data of switching signals for driving Insulated Gate Bipolar Transistors (IGBTSs) which are stored in MATLAB workspacs, are then used to be programmed in FPGA using a Quartus 11 software. Note that the generation of switching signals performed by FPGA is at the same sampling time in MATLAB. Using this approach, the computational burden of SVM can be greatly minimized and the desired output voltage can be obtained at high degree of accuracy. The simulation and experiment results are carried out to highlight at the advantages of using SVM and to verify the improvements of this approach by using FPGA controller. Some simulations and experiments were carried out to highlight the improvements, which are as follows; 1) the lower THD of the simulation result is about 14.37% for five-level CHMI and experiment result is about 14.35% for five- level CHMI at modulation index M; = 0.9, 2) the error percentage between the simulation and experimental results of the fundamental output voltage in SVM is small which is approximately less than 1 %, where the minimum error in two-level at M; = 0.9 is around 0.06% and the maximum error in five-level at M; = 0.3 is around 0.52%. The main benefit of this approach s to provide a high precision space vector modulator for cascaded Hbridge multilevel inverter for electric vehicle and Uninterruptible Power Supply (UPS) applications.

Item Type:	Thesis (Masters)
Uncontrolled Keywords:	Electric inverters, Space Vector Modulation, SVM, Cascaded H-Bridge, Multilevel Inverter, FPGA
Subjects:	T Technology > T Technology (General) T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:	Library > Tesis > FKE
Depositing User:	F Haslinda Harun
Date Deposited:	06 Jan 2022 12:03
Last Modified:	06 Jan 2022 12:03
URI:	http://eprints.utem.edu.my/id/eprint/25512
Statistic Details:	View Download Statistic

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