Mohd Nizam, Nur Hazwani Naili (2024) Development and optimization of Bi-GFET using Taguchi-based grey relational analysis with artificial neural network. Masters thesis, Universiti Teknikal Malaysia Melaka.
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Abstract
The semiconductor and electronics industries of micro-to-nano downscaling refer to the trend of miniaturizing electronic devices. The goal of this downscaling is to increase performance while reducing power consumption. However, it has become more complex because of their downscaling limit which possibilities to produce a short channel effect. To address this issue, an additional kind of MOSFET architecture with a double-gate design has been proposed to replace the single-gate MOSFET including replacing the SiO2/polysilicon gate with a high-k/metal gate to reduce the power consumption of the device. The implementation of bilayer graphene is employed to create a band gap, resulting in a greater on-off ratio. The purpose of this research is to develop the Bi-GFET horizontal double gate NMOS and PMOS device by using Silvaco Software's ATHENA and ATLAS modules and optimize it by using Taguchi-based grey relational analysis (GRA) with an artificial neural network (ANN). For the NMOS device, hafnium dioxide (HfO2) with tungsten silicide (WSix) will be utilized to examine the performance of the characteristics of the threshold voltage (VTH), drive current (ION), and leakage current (IOFF). Meanwhile, HfO2 with titanium silicide (TiSix) will be utilized in the PMOS device. In order to optimize the NMOS and PMOS device, the process parameters of VTH adjustment implant dose, VTH adjustment implant energy, S/D implant dose, and S/D implant energy were studied. The full potential of the Taguchi method as a tool for optimizing the performance of processes with a wide range of input variables has been realized. Based on the Taguchi results, S/D adjustment implant energy is identified as the dominant factor in the NMOS device with a contributing factor effect percentage of 89.77%, while VTH adjustment implant energy is identified as the dominant factor in the PMOS with a contributing factor percentage of 55.91%. To solve optimization problems with multiple responses of VTH, ION, and IOFF, GRA is used in conjunction with the Taguchi method in NMOS and PMOS devices. After optimization by using Taguchi-based GRA, the VTH, ION, and IOFF of the NMOS devices are observed to be at 0.20849 V, 5192.22 μA/μm, and 0.56513 nA/μm respectively. Meanwhile, the VTH, ION, and IOFF of the PMOS devices are observed to be at 0.19793 V, 167.873 μA/μm, and 32.5728 nA/μm respectively. The grey relational grade (GRG) of NMOS devices increased slightly by 3.44%, while the PMOS device was reduced by 0.86%. To forecast optimal optimization outcomes for the NMOS and PMOS devices a well-trained ANN is developed using the Levenberg-Marquardt algorithm. Results showed that VTH, IOFF, and ION values for NMOS devices met the prediction of the International Technology Roadmap Semiconductor (ITRS) with a value of 0.20987 V, 4979.58 μA/μm, and 0.10375 nA/μm respectively. For the PMOS device, VTH and IOFF met the prediction of the ITRS with the value of 0.20452 V, and 20.3584 nA/μm respectively, while the ION value is lower than the prediction with the value of 153.996 μA/μm due to the higher mobility of electrons resulting in a higher drain current.
| Item Type: | Thesis (Masters) |
|---|---|
| Uncontrolled Keywords: | Semiconductor industry, Electronics industry, Power consumption reduction |
| Divisions: | Library > Tesis > FTKEK |
| Depositing User: | Muhamad Hafeez Zainudin |
| Date Deposited: | 27 Dec 2024 15:56 |
| Last Modified: | 27 Dec 2024 15:56 |
| URI: | http://eprints.utem.edu.my/id/eprint/28323 |
| Statistic Details: | View Download Statistic |
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