Design and analysis of 22 nm DG-MOSFET with high-k metal gate graphene structure for better current performance

Yahaya, Izwanizam (2024) Design and analysis of 22 nm DG-MOSFET with high-k metal gate graphene structure for better current performance. Masters thesis, Universiti Teknikal Malaysia Melaka.

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Abstract

One of the innovations with the unique properties of graphene, which is frequently a complementary material of today's advanced materials technology, is the design process for the virtual fabrication of double layer graphene MOSFET 22 nm with high-k metal gate (HKMG). Aggressive scaling of MOSFET designs with channel lengths below 100 nm and oxide gate thicknesses below 3 nm is required to enhance performance and packaging density. As a result, several variables, such as threshold voltage, sub-threshold slope, ON current, and OFF current, significantly impact how well a device scales. Both devices were the focus of simulation work that was carried out and documented in publications. The TCAD fabrication tool from SILVACO software was used. Both the ATLAS and ATHENA simulation modules were used to create the device design and to describe the electrical characteristics of the device. Using the fixed field scaling method, it is possible to determine the electrical characterization of transistors according to international standards. Nano-sized transistors are produced using cutting-edge and novel techniques, which reduce production issues while enhancing transistor performance. Titanium dioxide (TiO2) and Tungsten Silicide (WSix) are used for the metal gate. Applying graphene to MOSFETs will increase current drive and decrease current leakage, hence improving electron mobility. Due to the connection between the graphene layer and the high-k metal gate, double gate (DG) MOSFETs are electrostatically superior to single gate (SG) MOSFETs, enabling further gate length scaling. A model that complies with the International Technology Roadmap for Semiconductor (ITRS) specification. The required VTH for logic technology high performance (HP) data should get the value is 0.206 ±12.7%V. The Taguchi method correctly predicted the best solution for fabricating the desired DG-MOSFET 22 nm with bilayer graphene. The primary response used to decide whether or not the designed device operates is the threshold voltage. One of the process variables that had the biggest impact on response characteristics in this study was the threshold voltage implant. The threshold voltage value for NMOS is 0.197858V and PMOS is -0.20744V. Both of these values are still within the ITRS standard range. Whereas for PMOS and NMOS devices, the S/D Implant Energy dose was identified as an adjustment factor to obtain nominal threshold voltage values of PMOS -0.206V ±12.7% and NMOS +0.206V ±12.7%, respectively. The ION value must be greater than 1469 uA/um, and the IOFF value must be less than 100 nA/um. This is achieved by performing experiments using designed arrays of MOSFETs, each with different design parameters, and then using statistical analysis to identify the ideal set of parameters. Taguchi's method has been successful in finding designs that minimize the variability of performance metrics, making devices more robust and predictable.

Item Type:	Thesis (Masters)
Uncontrolled Keywords:	Graphene, Double layer graphene MOSFET, High-k metal gate (HKMG)
Divisions:	Library > Tesis > FTKEK
Depositing User:	Muhamad Hafeez Zainudin
Date Deposited:	31 Jan 2025 16:27
Last Modified:	31 Jan 2025 16:27
URI:	http://eprints.utem.edu.my/id/eprint/28370
Statistic Details:	View Download Statistic

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